Initial Results on the Performance and Costof Vector

Increasinglywider superscalarprocessors are experiencingdi-minishing performance returns while requiring larger portions of die area dedicated to control rather than datapath. As an alternative to using these processors to exploit parallelismeeectively, we are investigating the viability of using single-chip vector microprocessors. This paper presents some initial results of our investigation where we compare the performance and cost of vector microprocessors to that of aggressive, out-of-order super-scalar microprocessors. On the performance side, we show that vector processors are able to execute a highly parallel, integer-based application 1.5{ 7.3 times faster than superscalar processors can by exploiting parallelism more eeectively. This ability stems from the use of vector instructions. Vector instructions exploit parallelism across loop iterations by implicitly rescheduling operations and temporally localizing the parallelism. Vector instructionsalso reduce instruction bandwidth by more than an order of magnitude because they express an abundance of parallelism in a compact encoding. On the cost side we show that, to achieve these performance gains, highly parallel, integer-based vector microprocessors are no more costly to implement than existing in-order and out-of-order superscalar microprocessors. One reason for this is that the organization of a vector register le provides tremendous bandwidth without incurring a large area penalty. A second reason is that the control logic for issuing vector instructions is relatively simple. Both the performance gains and cost savings are possible because vector processors rely on a vectorizing compiler, rather than hardware, to detect parallelism and to express it in a compact form to the hardware. These initial results suggest that transferring this functionality to the compiler ooers a tremendous performance/cost beneet.